1. Field of the Invention
The present invention relates generally to the field of semiconductor packaging, and more specifically to the interconnect between a C4 bump and a semiconductor die.
2. Discussion of Related Art
Presently, a semiconductor die is connected to a flip-chip package by a two dimensional array of C4 bumps. Power is routed through the package to the die via these C4 bumps. Power is further distributed from these C4 bumps to different parts of the die through metal interconnect lines in the top metal layers of the die.
FIG. 1 illustrates the connection between a C4 bump 102 and the top metal layer of the die 100. This connection is presently done through a single passivation opening, as illustrated in FIG. 1. C4 bump 102 is connected to a metal line 104 in the top metal layer through a single passivation opening 106. Typically, the C4 bump 102 has a diameter of 110 microns. The lines of the top metal layer are 20 microns wide, and the passivation opening 106 has an area of approximately 256 square microns (16 um×16 um).
Power is routed through the die by way of a number of metal layers. The top two metal layers are illustrated in FIG. 1. The metal lines 104 on the top metal layer distribute power to metal lines on lower metal layers, including metal lines 112 on the top-1 metal layer. Thus, power travels from a C4 bump 102, through a single passivation opening 106, to a top metal line 104 in the die, and is then routed to the top-1 metal layer lines 112 and other lower layer metal lines.
Current density and the ability for the power grid to reliably deliver current is a function of the metal stack and the EM (electromigration) capabilities of the metals and vias in the metal stack. Presently EM issues may be solved in several ways. For example, for a single passivation opening connection, when current crowding exceeds EM margins, an additional metal layer may be added to the metal stack to reduce current crowding, however this may increase the cost of manufacturing. Another alternative that may be used to reduce current crowding is to use a thicker metal layer or increase the pitch of the metal lines. This alternative may result in an undesirable reduction of signal routing capability. A further option is doping of the metal layers to allow for greater EM margins. Doping of the metal layers may increase the resistance of the metal lines, which is undesirable.